1. Field of the Invention
The method relates to a frequency detecting mechanism, and more particularly to a device having a frequency detector to detect frequencies and a method thereof.
2. Description of the Prior Art
Nowadays, electronic systems are getting more and more complicated. Electronic systems consist of many sub-electronic devices, in which each of the sub-electronic devices may operate at different operating frequencies. Furthermore, the operating frequency of a sub-electronic device may vary in accordance with the operating process of the electronic system, thus the role of a frequency detector becomes more important. On the other hand, the operating frequency of the electronic system is also getting faster in order to conform to a particular requirement, the resolution of the frequency detector must also be higher. In the prior art, a frequency detector having a high resolution but a simple configuration has not been attained. In other words, the prior art frequency detector is only able to discriminate a generally high frequency clock or a low frequency clock, but not able to detect a precise frequency value. Therefore, a frequency detector with simple configuration having wide bandwidth detection abilities is a goal of recent development.
The problem of the prior art is described more clearly in the following description. Normally, when a microprocessor is ready to access a memory, the microprocessor transmits a reading signal to the control circuit of the memory, wherein the reading signal is synchronized with an external clock. In addition, according to prior art, a latency counter is coupled between the microprocessor and the control circuit, for providing a delay time (delay clock period number) to the reading signal in order to guarantee that there is enough time for the memory to access the specific address. However, because of the wide operating frequency range of the memory, the latency counter needs to have a different delay clock period number at a high operating frequency from that at a low operating frequency.
In other words, when operating at a high operating frequency, the delay clock period number should be larger, but when operating at the low operating frequency, the delay clock period number should be smaller. However, the intrinsic delay of the circuit will affect the synchronization between the external clock and the reading signal. In other words, when operating at the high operating frequency, the intrinsic delay of the circuit may be higher than the clock period of the high operating frequency; thus the latency counter may output an error latency delay when the reading signal has slight non-synchronicity with the external clock, and the control circuit will read the error signal consequently.